TSMC Jumps into Silicon Photonics, Lays Out Roadmap for 12.8 Tbps Interconnect

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  "title": "TSMC Jumps into Silicon Photonics, Lays Out Roadmap for 12.8 Tbps Interconnect",
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  "url": "https://www.anandtech.com/show/21373/tsmc-adds-silicon-photonics-coupe-roadmap-128tbps-on-package"
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{
  "author": "Anton Shilov",
  "date": "2024-04-26T20:00:00.000Z",
  "description": "Optical connectivity – and especially silicon photonics – is expected to become a crucial technology to enable connectivity for next-generation datacenters, particularly those designed…",
  "image": "https://images.anandtech.com/doci/21373/council-bluffs-network-room_678x452.jpg",
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  "publisher": "AnandTech",
  "title": "TSMC Jumps Into Silicon Photonics, Lays Out Roadmap For 12.8 Tbps COUPE On-Package Interconnect",
  "url": "https://www.anandtech.com/show/21373/tsmc-adds-silicon-photonics-coupe-roadmap-128tbps-on-package"
}

{
  "url": "https://www.anandtech.com/show/21373/tsmc-adds-silicon-photonics-coupe-roadmap-128tbps-on-package",
  "title": "TSMC Jumps Into Silicon Photonics, Lays Out Roadmap For 12.8 Tbps COUPE On-Package Interconnect",
  "description": "optical connectivity – and especially silicon photonics – is expected to become a crucial technology to enable connectivity for next-generation datacenters, particularly those designed...",
  "links": [
    "https://www.anandtech.com/show/21373/tsmc-adds-silicon-photonics-coupe-roadmap-128tbps-on-package",
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  ],
  "image": "https://images.anandtech.com/doci/21373/council-bluffs-network-room_678x452.jpg",
  "content": "<section>\n<div>\n        <ul>\n            <li><a target=\"_blank\" href=\"https://www.anandtech.com/\">Home</a><span>&gt;</span></li>\n                <li><a target=\"_blank\" href=\"https://www.anandtech.com/tag/semiconductors\">Semiconductors</a></li>\n        </ul>\n</div>\n<div>\n                <p><img src=\"https://images.anandtech.com/doci/21373/council-bluffs-network-room_678x452.jpg\" />\n                </p>\n        <div>\n            <p>Optical connectivity – and especially silicon photonics – is expected to become a crucial technology to enable connectivity for next-generation datacenters, particularly those designed HPC applications. With ever-increasing bandwidth requirements needed to keep up with (and keep scaling out) system performance, copper signaling alone won't be enough to keep up. To that end, several companies are developing silicon photonics solutions, including fab providers like TSMC, who this week outlined its 3D Optical Engine roadmap as part of its 2024 North American Technology Symposium, laying out its plan to bring up to 12.8 Tbps optical connectivity to TSMC-fabbed processors.</p>\n<p>TSMC's Compact Universal Photonic Engine (COUPE) stacks an electronics integrated circuit on photonic integrated circuit (EIC-on-PIC) using the company's SoIC-X packaging technology. The foundry says that usage of its SoIC-X enables the lowest impedance at the die-to-die interface and therefore the highest energy efficiency. The EIC itself is produced at a 65nm-class process technology.</p>\n<p><a target=\"_blank\" href=\"https://images.anandtech.com/doci/21373/TSMC-3D-Optical-Engine.png\"><img src=\"https://images.anandtech.com/doci/21373/TSMC-3D-Optical-Engine.png\" /></a></p>\n<p>TSMC's 1st Generation 3D Optical Engine (or COUPE) will be integrated into an OSFP pluggable device running at 1.6 Tbps. That's a transfer rate well ahead of current copper Ethernet standards – which top out at 800 Gbps – underscoring the immediate bandwidth advantage of optical interconnects for heavily-networked compute clusters, never mind the expected power savings.</p>\n<p>Looking further ahead, the 2nd Generation of COUPE is designed to integrate into CoWoS packaging as co-packaged optics with a switch, allowing optical interconnections to be brought to the motherboard level. This version COUPE will support data transfer rates of up to 6.40 Tbps with reduced latency compared to the first version.</p>\n<p>TSMC's third iteration of COUPE – COUPE running on a CoWoS interposer – is projected to improve on things one step further, increasing transfer rates to 12.8 Tbps while bringing optical connectivity even closer to the processor itself. At present, COUPE-on-CoWoS is in the pathfinding stage of development and TSMC does not have a target date set.</p>\n<p>Ultimately, unlike many of its industry peers, TSMC has not participated in the silicon photonics market up until now, leaving this to players like GlobalFoundries. But with its 3D Optical Engine Strategy, the company will enter this important market as it looks to make up for lost time.</p>\n<h3><strong>Related Reading</strong></h3>\n<ul>\r\n\t<li><a target=\"_blank\" href=\"https://www.anandtech.com/show/21369/tsmcs-16nm-technology-announced-for-late-2026-a16-with-super-power-rail-bspdn\">TSMC's 1.6nm Technology Announced for Late 2026: A16 with \"Super Power Rail\" Backside Power</a></li>\r\n\t<li><a target=\"_blank\" href=\"https://www.anandtech.com/show/21370/tsmc-2nm-update-n2-in-2025-n2p-loses-bspdn-nanoflex-optimizations\">TSMC 2nm Update: N2 In 2025, N2P Loses Backside Power, and NanoFlex Brings Optimal Cells</a></li>\r\n\t<li><a target=\"_blank\" href=\"https://www.anandtech.com/show/21371/tsmc-preps-lower-cost-4nm-n4c-process-for-2025\">TSMC Preps Cheaper 4nm N4C Process For 2025, Aiming For 8.5% Cost Reduction</a></li>\r\n\t<li><a target=\"_blank\" href=\"https://www.anandtech.com/show/21372/tsmcs-system-on-wafer-platform-goes-3d-cow-sow\">TSMC's System-on-Wafer Platform Goes 3D: CoW-SoW Stacks Up the Chips</a></li>\r\n</ul>\n        </div>\n</div>\n            </section>",
  "author": "Anton Shilov",
  "favicon": "https://www.anandtech.com/favicon.ico",
  "source": "anandtech.com",
  "published": "2024-04-26t20:00:00z",
  "ttr": 85,
  "type": "article"
}